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description the a8601 is a fixed frequency, multiple-output supply for lcd bias. its switching frequency can be either programmed or synchronized with an external clock signal between 350 khz and 2.25 mhz, to minimize interference with am and fm radio bands. a total of five output voltages are provided, from three linear regulators and two charge-pump regulators. each output voltage can be adjusted independently. during power-up and shutdown, the outputs are turned on and off in preprogrammed sequences, to meet the sequencing requirements for specific lcd panels. short circuit protection is provided for all outputs. the boost switch is protected against overcurrent and overvoltage. input disconnect protection is achieved by driving an external p-mosfet. 28-pin exposed thermal pad tssop package allows operation at high ambient temperatures. it is lead (pb) free with 100% matte-tin leadframe plating. a8601-ds, rev. 1 features and benefits ? automotive grade aec-q100 qualified ? five individual output supplies ? independent control of each output voltage ? 350 khz to 2.25 mhz switching frequency with external synchronization capability ? <10 a shutdown current ? preprogrammed power-up and shutdown sequences ? overcurrent, overvoltage, short circuit, and thermal overload protection multiple-output regulator for automotive lcd displays package: 28-pin tssop with exposed thermal pad (suffix lp) system block diagram not to scale a8601 applications: ? gps ? infotainment ? medium lcds en1 en2 fset_sync 1.5 to 3.2 v vinamp lcd panel output voltages shown are for typical lcd panel external sync vcom v vcom 3 to 6 v vgl vgh avdd dvdd a8601 vin v vin vin ins gate sw d1 l1 q1 optional r sc out fault + v vgl ? 5 to ?12 v + + v avdd 5 to 14 v v vgh 10 to 25 v v dvdd 3.3 v
multiple-output regulator for automotive lcd displays a8601 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings 1,2 characteristic symbol notes rating unit vin and ins pin voltage v vin , v ins all voltages measured with respect to gnd ?0.3 to 6.5 v sw pin voltage 3,4 v sw continuous ?0.6 to 22 v voltage spikes (pulse width < 100 ns) ?1 to 40 v out pin voltage v out ?0.3 to 22 v avdd and fb2 pin voltage v avdd , v fb2 ?0.3 to v out + 0.3 v cp11 pin voltage v cp11 positive charge pump ?0.3 to v cp12 + 0.3 v cp12 pin voltage v cp12 positive charge pump ?0.3 to 27 v vgh pin voltage v vgh positive charge pump ?0.3 to 27 v fb4 pin voltage v fb4 positive charge pump ?0.3 to v vgh + 0.3 v cp21 pin voltage v cp21 negative charge pump ?0.3 to 14 v cp22, vgl and fb3 pin voltage v cp22 , v vgl , v fb3 negative charge pump ?14 to 0.3 v en1, en2, and f a u l t pin voltage v en1 , v en2 , v fault ?0.3 to 5.5 v bias pin voltage v bias ?0.3 to lower of: 5.5 or v vin + 0.3 v vcom pin voltage v vcom ?0.3 to lower of: 7 or v avdd + 0.3 v pgnd and gndvcom pin voltage v pgnd , v gndvcom ?0.3 to 0.3 v all other pins 5 ? ?0.3 to 7 v operating ambient temperature t a k temperature range ?40 to 125 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc 1 stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ra tings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characte ristics table is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device reliability. 2 all voltages referenced to agnd. 3 the sw pin has internal clamp diodes to gnd. applications that forward bias this diode should take care not to exceed the ic pa ckage power dissipation limits. note: exact energy specification to be determined. 4 the switch dmos is self-protected. if voltage spikes exceeding 40 v are applied, the device would conduct and absorb the energy safely. 5 when v vin = 0 (no power), all inputs are limited by -0.3 to 5.5 v. thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja on 4-layer pcb based on jedec standard 28 oc/w *additional thermal information available on the allegro website. selection guide part number packing* programming A8601KLPTR-T 4000 pieces per 13-in. reel contact allegro sales for vcom regulator factory trim option *contact allegro ? for additional packing options.
multiple-output regulator for automotive lcd displays a8601 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table of contents characteristic performance 10 functional description 15 linear regulators 15 vcom regulator 15 charge pumps 16 boost controller 18 switching frequency 19 continuous conduction mode operation 20 input disconnect switch 21 fault conditions 22 pre-output fault detection 23 general fault detection 23 application information 24 output voltage selection 24 output capacitance 25 operating with separate vin and boost supplies 26 thermal analysis 26 component selection recommendations 28 i/o pin equivalent circuit diagrams 29
multiple-output regulator for automotive lcd displays a8601 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram drive ocp ldo 1 2 5 3 4 1 to 5 6 6 6 6 6 6 reg boost regulator with soft start fault v in bias regulator 3.6 v on on off off enable/ disable off off off 10 % + - on off + ? 90 % + ? 90% on on inverted charge pump 2x charge pump on + ? x1.94 op amp ldo ins vin dvdd fb1 en1 fset_sync comp c comp en2 bias agnd gate sw out c out avdd fb2 vinamp vcom c vcom c avdd gndvcom cp11 c fly1 c fly2 cp12 vgh fb4 cp21 cp22 vgl fb 3 pgnd d1 l1 q1 r sc 5 v dc to dc converter ( min. 4v ) v dvdd 3.3 v . external sync v avdd 10v output voltages shown are for a typic al lcd panel see terminal list table 18 v v vgl v vgh -8 v v vin + + 1.5 to 3.2 v from microprocessor + + v vcom 3 to6 v fault
multiple-output regulator for automotive lcd displays a8601 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram terminal list table number name function 1 gate gate driver for input disconnect p-mosfet 2 ins high-side sense for input overcurrent detection 3 vin input supply voltage (4.0 to 5.5 v) for the ic 4 dvdd output from internal ldo (item 1 in functional block diagram) powered by vin 5 fb1 (dvdd) connect to resistor divider network to set dvdd 6 comp compensation pin, connect to external comp capacitor 7 vinamp control voltage from external microprocessor 8 vcom output from operational amplifier (item 5 in functional block diagram), controlled by vinamp 9 gndvcom ground reference for vcom 10 fset_sync input for synchronizing boost and charge pump signals switching frequency to external clock signal; alternatively, it can be connected to an external resistor to set the switching frequency 11 bias output from internal 3.6 v bias regulator; connect to gnd via 0.1 f ceramic capacitor 12 f a u l t open-drain output, pulls low in error condition 13 en1 enable pin for dvdd output; system can only be enabled after v vin is above uvlo level (refer to startup timing diagram) 14 en2 enable pin for the voltage outputs other than dvdd; it can be activated only after v vin is above uvlo and en1 = high. gate ins vin dvdd fb1 comp vinamp vcom gndvcom fset_sync bias fault en1 en2 sw pgnd out avdd fb2 cp11 cp12 vgh fb4 cp21 cp22 vgl fb3 agnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pad number name function 15 agnd analog gnd reference for signals; connect to ground plane 16 fb3 (vgl) connect to resistor divider network to set v vgl 17 vgl inverted charge pump output (item 3 in functional block diagram) 18 cp22 capacitor terminal for inverted charge pump (item 3 in functional block diagram); refer to negative charge pump section for usage 19 cp21 capacitor terminal for inverted charge pump (item 3 in functional block diagram) 20 fb4 (vgh) connect to resistor divider network to set v vgh 21 vgh 2x charge pump (item 4 in functional block diagram) output 22 cp12 capacitor terminals for charge pump (item 4 in functional block diagram) 23 cp11 24 fb2 (avdd) connect to external resistor network to set v avdd 25 avdd output from internal ldo (item 2 in functional block diagram) powered by v out 26 out connect to boost output for internal ldo and charge pump regulators 27 pgnd power ground for internal boost switch; connect this pin to ground terminal of output ceramic capacitor(s) 28 sw boost converter switch node ? pad exposed pad (substrate of ic); solder to gnd plane for better thermal conduction
multiple-output regulator for automotive lcd displays a8601 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com continued on the next page? electrical characteristics 1 valid at v vin = 5 v, en1 = en2 = high, f sw = 2 mhz, v dvdd = 3.3 v, v avdd = 10 v, v vgh = 20 v, v vgl = ?8 v, t j = t a = 25c, except indicates specifications guaranteed for t j = t a = ? 40c to 125c; unless otherwise specified characteristics symbol test conditions min. typ. max. unit input voltage and current input voltage v vin 4.0 ? 5.5 v vin pin undervoltage lockout (uvlo) threshold v uvlo v vin rising 3.6 ? 4.0 v vin pin uvlo hysteresis v uvlo(hys) ? 0.15 0.25 v shutdown bias current i vinbias(sd) current into vin pin, en1 = low ?550 a standby bias current i vinbias(stb) en1 = high, en2 = low, no load at dvdd pin ? 2 ? ma operating bias current i vinbias(op) en1 = high, en2 = high ? 6.5 ? ma boost switch switch peak current limit i sw(max) cycle-by-cycle current limit 1.3 ? 2.0 a switch on-resistance r ds(on) i sw = 0.5 a ? 0.5 ? switch minimum on-time t on(min) 50 72 95 ns switch minimum off-time t off(min) 33 50 75 ns sw pin leakage current i sw(lkg) v sw = 5 v, en1 = low ? 0.1 ? a out pin leakage current i out(lkg) v out = 5 v, en1 = low ? 0.1 ? a sw pin secondary overvoltage protection (ovp) v sw(ovp) 17.4 19.2 21.2 v sw pin secondary ovp minimum pulse width 4 t sw(ovp) v sw ovp level ? 40 ? ns switching frequency / synchronization fset_sync pin voltage v fsetsync without using external synchronization signal ? 1.0 ? v fset_sync pin current i fsetsync 34 ? 220 a switching frequency f sw r fset_sync = 5.1 k 1.81 2.0 2.17 mhz synchronization frequency f sync external logic signal connected to fset_sync pin 0.35 ? 2.25 mhz synchronization minimum on-time t sync(on) 150 ? ? ns synchronization minimum off-time t sync(off) 150 ? ? ns input disconnect gate pin sink current i gate(snk) v gate = v vin , no fault ? 100 ? a gate pin source current i gate(src) v gate = 0 v, fault tripped ? 130 ? ma gate voltage at off condition v gate(off) en1 = en2 = low, or fault tripped ? v vin ?v ins trip point v ins(trip) between vin and ins pins 85 100 115 mv ins trip blanking time t ins(blank) sensed voltage = 2 input current limit 1.5 ? 3 s
multiple-output regulator for automotive lcd displays a8601 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 (continued) valid at v vin = 5 v, en1 = en2 = high, f sw = 2 mhz, v dvdd = 3.3 v, v avdd = 10 v, v vgh = 20 v, v vgl = ?8 v, t j = t a = 25c, except indicates specifications guaranteed for t j = t a = ? 40c to 125c; unless otherwise specified characteristics symbol test conditions min. typ. max. unit continued on the next page? feedback pins feedback sense voltage v fbx fb1, fb2, and fb4 pins ? 2.40 ? v fb3 pin ? ?1.8 ? v output overvoltage fault threshold v fbx(ov) fb1, fb2, and fb4 pins; v fbx rising ? 2.88 ? v v fb3 falling ? ?2.16 ? v output undervoltage fault threshold v fbx(uv) fb1, fb2, and fb4 pins; v fbx falling ? 1.92 ? v v fb3 rising ? ?1.44 ? v feedback input currents i fbx fb1, fb2, and fb4 pins; v fbx = 2.4 v ? ?0.5 ? a v fb3 = ?1.8 v ? 0.5 ? a feedback load resistance 2 r fbx fb1 pin 9 10 11 k fb2 pin 24 25 26 k fb3 and fb4 pins 49 50 51 k output regulators dvdd output voltage v dvdd v vin = 4.0 to 5.5 v 2.4 ? v vin ? 0.6 v avdd output voltage v avdd v vin = 4.0 to 5.5 v 4.4 ? 14.8 v vcom output voltage v vcom v vin = 4.0 to 5.5 v, v avdd > v vcom + 1.5 v 2.9 ? 6.8 v vgh output voltage v vgh v vin = 4.0 to 5.5 v 2.4 ? 26 v vgl output voltage v vgl v vin = 4.0 to 5.5 v ?12.9 ? ?5 v dropout for dvdd regulator v dvdd(do) between vin and dvdd pins; v fb1 = 2.33 v, i out = 50 ma ? ? 0.6 v boost minimum headroom for avdd regulator v avdd(do) defined as v out ? v avdd ; v fb2 = 2.33 v, i out = 100 ma ?2?v boost minimum headroom for vgh regulator v vgh(do) defined as v out ? v vgh / 2; v fb4 = 2.33 v, i out = 8 ma ? 2.4 ? v boost minimum headroom for vgl regulator v vgl(do) defined as v out ? (?v vgl ); v fb3 = ?1.75 v, i out = ?8 ma ? 3.6 ? v output pull-down resistor during shutdown (avdd, vcom, vgh, vgl) r outpd en1 = high, en2 = low ? 250 ? logic inputs input logic high v ih en1, en2, fset_sync pins 1.8 ? ? v input logic low v il en1, en2, fset_sync pins ? ? 0.8 v internal pull-down resistance to agnd r enx(pd) en1, en2 pins ? 100 ? k
multiple-output regulator for automotive lcd displays a8601 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com output current capacity dvdd overcurrent protection (ocp) trip level i dvdd(ocp) 50 ? 90 ma avdd ocp trip level i avdd(ocp) includes i vcom 200 ? 350 ma vcom ocp trip level i vcom 60 ? 110 ma vgh ocp trip level i vgh 14 ? 32 ma vgl ocp trip level i vgl current into vgl pin 14 ? 32 ma output voltage accuracy dvdd load regulation v dvddreg v dvdd = 3.3 v, i load = 10 to 50 ma ?0.1 ? 0.1 v avdd, vgl and vgh load regulation v xreg i load = 10% to 100% of i x(ocp) (min) ?0.1 ? 0.1 v dvdd accuracy 3 err dvdd v dvdd = 3.30 v ?2.5 ? 2.5 % avdd accuracy 3 err avdd v avdd = 10.0 v ?2.1 ? 2.1 % vgh accuracy 3 err vgh v vgh = 20.0 v ?2.5 ? 2.5 % vgl accuracy 3 err vgl v vgl = ?8.0 v ?2.5 ? 2.5 % vcom operational amplifier vcom gain 4 a vcom defined as v vcom / v vinamp ; 1.5 v < v vinamp < 3.21 v, ?30c < t a < 85c, i load = 25 ma 1.92 1.94 1.96 v / v vcom load regulation 4 v vcomreg i load = 5 to 50 ma ?5 ? 5 mv vcom temperature coefficient 4 tc vcom ?30c < t a < 85c, i load = 25 ma ?50 ? 50 v/c input resistance to agnd r vinamp(pd) vinamp pin ? 100 ? k dropout for vcom from avdd v vcom(do) v avdd = 7 v, i vcom = 60 ma ? ? 1.5 v f a u l t pin f a u l t pull-down voltage v fault(pd) fault condition asserted, pull-up current = 1 ma ? ? 0.4 v f a u l t pin leakage current v fault(lkg) fault condition cleared, pull-up to 5 v ? ? 1 a electrical characteristics 1 (continued) valid at v vin = 5 v, en1 = en2 = high, f sw = 2 mhz, v dvdd = 3.3 v, v avdd = 10 v, v vgh = 20 v, v vgl = ?8 v, t j = t a = 25c, except indicates specifications guaranteed for t j = t a = ? 40c to 125c; unless otherwise specified characteristics symbol test conditions min. typ. max. unit continued on the next page?
multiple-output regulator for automotive lcd displays a8601 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 (continued) valid at v vin = 5 v, en1 = en2 = high, f sw = 2 mhz, v dvdd = 3.3 v, v avdd = 10 v, v vgh = 20 v, v vgl = ?8 v, t j = t a = 25c, except indicates specifications guaranteed for t j = t a = ? 40c to 125c; unless otherwise specified characteristics symbol test conditions min. typ. max. unit fault timers soft start time-out t ss(to) maximum time allowed for any output to reach 90% of its target 40 50 60 ms shutdown time-out t sdn(to) maximum time allowed for vgh to fall to 10% and vgl to 30% of their respective targets; en1 = high, en2 = low 40 50 60 ms overcurrent protection (ocp) time-out t ocp(to) maximum time allowed for any output to stay in an overcurrent fault condition before shutdown 40 50 60 ms restart delay t restart delay time after fault shutdown until the next retry (repeats until fault counter = 8) 80 100 120 ms fault counter reset time t fault time required after setting en1 = low until fault counter clears 1?? s thermal shutdown (tsd) protection tsd threshold t tsd temperature rising ? 165 ? c tsd hysteresis 4 t tsd(hys) ?20?c 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). 2 net parallel resistance required at fbx pin in order to meet accuracy. 3 output voltage is set to required nominal value using external sense resistor network. output current at 50% of minimum ocp tri p level. accuracy does not include mismatch error caused by external sense resistor network. 4 ensured by design and characterization, not production tested.
multiple-output regulator for automotive lcd displays a8601 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance startup and shutdown sequences (normal operation) vin dvdd en1 vgl vgh vinamp en2 avdd 90% 90% 90% vcom 30% 10% 90% t<100 ms notes: ? normal system startup should follow the above sequence (vin en1 en2). ? en1 can only be asserted after vin is above uvlo level, v uvlo . if asserted before that, it is ignored until vin rises above v uvlo . ? en2 can only be asserted when dvdd is >90% target voltage. if asserted before that, it is ignored until the condition is met. ? vgh is enabled only after the magnitude of vgl has reached >90% of its target voltage. ? vcom output is enabled only after vgh has reached >90% of its target voltage. (a valid vinamp must be asserted prior to this.) ? system shutdown should start with en2 = low, followed by en1 = low. ? vgl shutdown can only start after vgh has dropped to 10% its original target voltage, or the vgh shutdown time-out interval has expired. ? en1 = low can only be asserted when vgl has fallen below 30% of its target voltage. if asserted before that, it is ignored until the condition is met or the vgl shutdown time-out interval has expired.
multiple-output regulator for automotive lcd displays a8601 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com startup and shutdown sequences (irregular) vin dvdd en1 vgl vgh vinamp en2 avdd 90% 90% 90% vcom vin dvdd en1 vgl vgh vinamp en2 avdd vcom vin dvdd en1 vgl vgh vinamp en2 avdd vcom 90% 90% 90% v uvlo 30% 10% 90% 90% notes: ? case 1 (startup). during a startup sequence, if en2 goes high before en1 goes high, en2 is ignored until en1 also goes high and dvdd has risen to 90% of its target voltage. ? case 2 (startup). during a startup sequence, while vin is below the uvlo level, v uvlo , the ic is in sleep mode. if either en1 or en2 goes high while the ic is still in sleep mode, they are ignored until vin exceeds v uvlo . ? case 3 (shutdown). during a shutdown sequence, if en1 goes low before en2 goes low, en1 is ignored until en2 also goes low and vgl has fallen to 30% of its target voltage, or the vgl shutdown time-out interval has expired. case 1 (startup) case 2 (startup) case 3 (shutdown)
multiple-output regulator for automotive lcd displays a8601 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com notes: ? startup ramps are based on internal timing and are assumed to have 20% variation. ? an internal pull-down resistor of 250 is applied to each of the regulator outputs avdd, vgl, vgh, and vcom as soon as en1 = high. that means if any output capacitor was previously charged, it would be discharged by this pull-down resistor. the pull-down is removed just before each regulator is enabled. startup timing diagram en1 dvdd 90% en2 en2 ignored avdd 90% vgl 90% vgh 4 ms for 24 f capacitor loading 3 ms for 48 f capacitor loading 4 ms for 48 f capacitor loading 12 ms for typical capacitor loading 4 ms for 10 f capacitor loading 2 ms for 10 f capacitor loading vcom 90% 90% en1 ignored >100 s (determined by gate pin capacitance) ic waits until gate pin < (v vin ? 3.5 v)
multiple-output regulator for automotive lcd displays a8601 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com notes: ? all exponential decays are based on external capacitance and internal pull-down resistance (250 each for avdd, vcom, vgh, and vgl). the external dc load is assumed to be off or negligible. ? if any of the outputs avdd, vcom, or vgh does not decay to below 10% of target voltage after 50 ms, starting from en2 is low, it is by-passed and the rest of the shutdown sequence continues without it. ? for vgl, the shutdown detection threshold is set at 30%. only if the magnitude of vgl has dropped below 30%, when en1 goes low the ic will shut down completely. after shutdown, all internal pull-down resistors are released, and output capacitor voltages will decay according to external load resistances. shutdown timing diagram en2 avdd dvdd 10% 10% 10% 30% en1 en1 ignored vgl vgh device enters sleep mode 22 ms for 40 f capacitor discharge 6 ms for 10 f capacitor discharge 6 ms for 10 f capacitor discharge 7 ms for 24 f capacitor discharge cumulative 13 ms capacitor discharge for 10 f on vgh and 24 f on vgl en1 active after avdd, vgh, and vcom decay to <10%, and vgl decays to <30%, of their target values vcom
multiple-output regulator for automotive lcd displays a8601 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical load current during normal operation 500 ma avdd i avdd(av) = 140.25 ma 100 ma 3.2 s3.2 s 31.8 s 30 ma vgh i vgh(av) = 7.9 ma 4 ma 4.8 s4.8 s 31.8 s 30 ma vgl i vgl(av) = 8.9 ma 4 ma 6 s6 s 31.8 s 50 ma vcom i vcom(av) = 18.3 ma 15 ma 6 s6 s 63.6 s
multiple-output regulator for automotive lcd displays a8601 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description the a8601 is a flexible multi-voltage regulator designed for lcd panel bias applications. it utilizes a high-efficiency boost converter, together with space-saving low-dropout regulator and charge pump circuits to provide five independently-adjustable voltage outputs: ? dvdd: typically 3.3 v. nominal output current 20 ma, maximum 100 ma. this output is from a low-dropout regulator (item 1 in the functional block diagram) powered by vin. it is available while en1 is high. ? avdd: typically between 5 and 13.3 v. nominal current 100 ma. this output is from a low-dropout regulator (item 2 in the functional block diagram) powered by vout. it is only available when both en1 and en2 are high. ? vcom: typically between 3 and 6 v at 50 ma. this voltage is programmable by applying a control voltage at the vinamp pin (1.5 to 3.2 v from the application microprocessor). the power supply of this regulator is internally connected to avdd. ? vgl: typically between ?11 and ?5.4 v at 4 ma. this voltage is generated by an inverted charge pump, which is powered by vout. ? vgh: typically between 14.5 and 24.6 v at 4 ma. this voltage is generated by a 2x charge pump, which is powered by vout. linear regulators the a8601 uses low-dropout linear regulators (ldo) to pro- vide dvdd from vin, and avdd from boost output voltage. a representative block diagram is shown in figure 1. each ldo is protected against output short or over-loading by its own internal ocp limits. refer to the fault conditions section for details. the avdd circuit monitors the voltage drop across its ldo (item 2 in the functional block diagram). if this voltage drop is less than 2 v, the avdd circuit sends a control signal to cause the boost voltage to increase. this ensures there is always enough headroom for regulation. vcom regulator the vcom output voltage is determined by the input voltage of vinamp (see figure 2), according to the following relation: v vcom = v vinamp 1.94 (1) rsc ocp from boost output pmos avdd 2.4 v enable avdd regulator a8601 agnd fb2 30 k fold back v vin 5 k discharge 250 to boost controller + ? + ? + ? rsc ocp from avdd pmos vcom enable vcom regulator a8601 gndvcom vinamp fold trimmed resistor divider back v out discharge 250 100 k to boost controller + ? + ? figure 1. representative linear regulator (avdd shown) figure 2. vcom regulator
multiple-output regulator for automotive lcd displays a8601 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the valid range for vinamp is between 1.5 and 3.2 v, which gives a v vcom range of 2.9 to 6.2 v (provided that avdd is at least 1.5 v higher than v vcom ). beyond this range, the linearity of vcom cannot be guaranteed. the supply voltage of vcom is taken from avdd. in order to ensure there is enough headroom, avdd must be at least 1.5 v higher than vcom . during the startup sequence, vcom is allowed to ramp up only after vgh has reached 90% of its target voltage. a valid vinamp must be asserted prior to vcom ramp up. if vinamp starts low (< 1.2 v), the a8601 waits as long as 50 ms for a valid vinamp to be asserted. if vinamp is not asserted by that time limit, a fault is generated. if vcom is not required, the vcom pin can be left open, but a small output capacitor (approximately 0.1 f) must be present to prevent oscillation. make sure to connect vinamp to a suitable voltage such as dvdd at 3.3 v. the connection to dvdd can be divided as shown in figure 3, according to the avdd level required. charge pumps the a8601 uses a 2x charge pump to generate vgh from boost voltage, and an inverting charge pump to generate vgl . repre- sentative block diagrams are shown in figure 4. the frequency of the charge pumps is the same as the boost switching frequency (or external sync frequency) when an external sync signal is used, it is internally converted into a clock signal with the same frequency, but at 50% duty cycle. recommended values of the external flying capacitor, c flyx , on 100 k a8601 vinamp gndvcom c vcom 0.1 f dvdd 3.3 v avdd >7 v 100 k a8601 vinamp 2.45 v gndvcom c vcom 0.1 f dvdd 3.3 v 10 k 40.2 k avdd 5 v figure 3. configuration for unused vcom: (upper panel) v avdd > 7 v, and (lower panel) v avdd = 5 v.
multiple-output regulator for automotive lcd displays a8601 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ocp from boost output s1 s2 cp21 c fly2 enable vgl regulator linear regulator 1x charge pump a8601 fb3 1.8 v discharge 250 to boost controller + ? agnd cp22 d3 (si) d1 d2 (si) vgl switching sequence: ? s1 closed and d3 charges c fly2 ? s2 closed and d2 dumps c fly2 to vgl + ocp from boost output s1 s2 cp21 c fly2 enable vgl regulator linear regulator 1x charge pump a8601 fb3 1.8 v discharge 250 to boost controller + ? agnd cp22 d1 d2 (si) vgl switching sequence: ? s1 closed and d1 charges c fly2 ? s2 closed and d2 dumps c fly2 to vgl + ocp from boost output s1 s2 cp12 c fly1 enable vgh regulator linear regulator 2x charge pump a8601 fb4 2.4 v discharge 250 5 k 55 k to boost controller + ? agnd cp11 d2 vgh d1 switching sequence: ? s1 closed and d1 charges c fly1 ? s2 closed and d2 dumps c fly1 to vgh + v vin figure 4c. inverting (negative) charge pump for vgl regulator, ac version full output current (14 ma) figure 4b. inverting (negative) charge pump for vgl regulator, ac version figure 4a. 2x charge pump for vgh regulator
multiple-output regulator for automotive lcd displays a8601 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the cpxx pins depends on the switching frequency as shown in the following table; a voltage rating of 25 v is sufficient: switching frequency (mhz) c flyx ( f) 2 0.1 1 0.22 0.350 0.47 for the inverted (negative) charge pump, an external silicon diode is used between the vgl and cp22 pins. however, at high tem- peratures and switching frequencies (such as 125c and 2 mhz), the maximum vgl output current is limited to about 8 ma. to achieve the full output current, 14 ma, it is necessary to use two external diodes, as shown in figure 4c. the value of the flying capacitor can be calculates as follows: 1. the equivalent series resistance of the flying capacitor is: esr fly2 = 1 / ( f sw c fly2 ) (2) 2. assuming a flying capacitor ripple voltage of 100 mv, and a maximum output current of 20 ma, the series resistance is: r fly2 = 0.1 (v) / 0.02 (a) 5 3. therefore at an f sw of 2 mhz, the required capacitance, c fly2 , is 0.1 f. boost controller the a8601 contains an integrated dmos switch and pwm controller to drive a boost converter. the input voltage, v vin , (5 v nominal) is boosted to an intermediate voltage, v out , which is the lowest voltage required to keep all outputs within regula- tion. that is, the effective boost voltage is the highest of the boost requirement of the individual regulators, as illustrated in figure 5. for example: assume the output requirements for a certain lcd panel are: v avdd = 10 v, v vgh = 18.5 v and v vgl = ?7 v, then: ? avdd (ldo 2): v out v avdd + 2 (v) = 12 v ? vgh (2x charge pump): v out 0.5 v vgh + 2.4 (v) = 11.65 v ? vgl (inverted charge pump): v out ? v vgl + 3.6 (v) = 10.6 v in this example, avdd has the highest requirement, so the intermediate voltage will be regulated at a v out of 12 v approxi- mately. however, if v vgh were increased to 23 v, it would be the highest, and then the boost converter would increase the interme- diate voltage to 13.9 v to satisfy the charge pump circuit. 0 2 4 6 8 10 12 14 16 -12-10-8 -6 -4-2 0 2 4 6 8 101214161820222426 boost voltage, v boost (v) regulated output (v) v boost(vgl) v boost(avdd) v boost(vgh) ( ?v vgl + 3.6 v) (v avdd + 2 v) (v vgh / 2 + 2.4 v) figure 5. boost voltage requirement with respect to vgl, avdd, and vgh
multiple-output regulator for automotive lcd displays a8601 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a block diagram of the a8601 boost controller circuit is shown in figure 6. the external comp capacitor, c comp , is typically a 0.1 to 1 f mlcc. the controller is protected against overvoltage and overcurrent fault conditions. ? the ovp threshold, v sw(ovp) , is internally set at approximately 19 v typical. under normal operating conditions, the boost volt- age should always be lower than 16 v (as shown in figure 5), so only in the event of a fault will ovp be tripped (for example: output diode open, or wrong sense resistor values). ? the switching current limit, i sw(max) , is protected by a pulse- by-pulse ocp threshold (1.5 a typical). in the event of a heavy load or during a transient, the sw peak current may reach ocp level momentarily. in this case, the present on-time period is terminated immediately, but no signal is generated on the f a u l t pin. ? in the event of a catastrophic failure (such as shorted inductor), the sw current may exceed 150% of the ocp threshold. in this case, the ic is shut down immediately. switching frequency the boost stage switching frequency, f sw , of the a8601 can be programmed by using an external resistor between the fset_sync pin to gnd, or it can be synchronized to an exter- nal clock frequency between 350 khz and 2.25 mhz. during startup, the a8601 senses the fset_sync pin for any external sync signal. if periodic logic transitions are detected (low < 0.8 v or high > 1.8 v), this is evaluated as an external clock signal, and the boost switching frequency is synchronized to it. if no periodic signal is detected, the bias current flowing through fset_sync pin is used to determine the switching fre- quency. the bias current is set by an external resistor, r fset , on the fset_sync pin. the relation between r fset and switching frequency is given as: r fset = 10.21 / ( f sw ? 0.0025) (3) where r fset is in k and f sw is in mhz. this relationship is charted in figure 7. for example, to get a switching frequency of 2 mhz requires an r fset of 5.11 k . enable a8601 pwm control slope compensation multi-input transconductance amplifier g m oscillator ovp dmos r sc sw pgnd comp c comp avdd vgh vgl + ? ocp figure 6. boost controller circuit figure 7. switching frequency versus fset resistance 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 5 10 15 20 25 30 f sw (mhz) r fset (k )
multiple-output regulator for automotive lcd displays a8601 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com suppose the a8601 is started up with a valid external sync sig- nal, but the sync signal is lost during normal operation. in that case, one of the following happens: ? if the external sync signal is high impedance (open), the a8601 continues normal operation, at the switching frequency set by r fset . no f a u l t flag is generated. ? if the external sync signal is low (shorted to ground), the a8601 begins a shutdown sequence, at the switching frequency set by the internal 1 mhz oscillator. the f a u l t pin is pulled low and the internal error counter is increased by 1. note: if the outcome of the second scenario is not acceptable, the circuit shown in figure 8 can be used to prevent generating a fault when the external sync signal goes low. when the circuit is used, after the external sync signal goes low, the a8601 will continue to operate normally at the switching frequency set by r fset . no f a u l t flag is generated. continuous conduction mode operation it is often preferable for a boost converter to operate in continu- ous conduction mode (ccm) in order to reduce switching noise and input ripple. however, whether the converter can operate in ccm or discontinuous conduction mode (dcm) is determined by many parameters, including input/output voltages, output current, switching frequency, and inductor value. this is explained as fol- lows, using simplified basic equations for a boost converter (refer to figure 9): during sw on-time, t on : i ripple = v vin / l t on (4) = v vin / l t d (5) where t is the switching period of the boost converter and d is the duty cycle, t on / t. during sw off-time, t off : i ripple = ( v out + v d1 ? v vin ) / l t off (5) = ( v out + v d1 ? v vin ) / l t (1 ? d ) (7) therefore: v out + v d1 = v vin 1 / (1 ? d ) (8) in order to operate in ccm, the minimum inductor current must be greater than zero amperes. this means: i sw (min) = i sw (av) ? i ripple / 2 0, or (9) i ripple 2 i sw (av) average input current is directly related to the input power and voltage, as given by: i sw (av) = p vin / v vin = ( p out / ) / v vin (10) where is the efficiency of the boost converter (typically around 80%). ripple current is determined by inductance, period, and duty cycle, as given by: i ripple = v vin / l t d (11) where d is 1 ? v vin /(v out + v d1 ) from equation 8. figure 8. low fset_sync signal fault counteraction circuit figure 9. continuous and discontinuous conduction mode factors external synchronization signal 220 pf a8601 fset_sync schottky barrier diode r fset 10.2 k pgnd ld1 a8601 sw out v out c out c vin vin dmos v sw i sw t on t off i ripple i sw (max) i sw (av) i sw (min) t t 0 v out +v d switching period, t
multiple-output regulator for automotive lcd displays a8601 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 100 mv 3.5 v 100 a ld a8601 vin v in fault gate_ok overcurrent ins gate sw out v out c out c gs (optional) r ins v s + ? + ? + ? + ? 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 inductance ( h) output voltage (v) p out = 1 w p out = 1.33 w p out = 2 w figure 11. input disconnect switch circuit figure 10. minimum inductance for ccm as a function of output voltage (at v vin = 5.5 v and f sw = 1 mhz) for a given v vin and v out , the duty cycle is fixed. furthermore, for a given output power, the average input current also is fixed. therefore the only way to reduce ripple current is either to switch at a higher frequency (a shorter period) or to use a larger induc- tance. figure 10 shows that the minimum inductance required to ensure ccm operation increases with higher output voltage (hence also with higher duty cycle), for a boost regulator with fixed input voltage and output power. note that the chart is calculated at an f sw of 1 mhz. if the frequency is reduced by half, to 500 khz, the inductance requirement is doubled. when selecting the boost inductor, pay attention to the following parameters: ? inductance. this usually determines whether the boost converter operates in dcm or ccm. refer to figure 10, or calculate mini- mum required inductance using the equations provided. ? dcr. lower resistance is preferred to reduce conduction loss. ? saturation current. i sat should be greater than 1.5 a, and prefer- ably 2 a. ? heating current. i heating should be greater than 1.5 a rms ? physical size. smaller size typically means lower i sat and higher dcr. the minimum sw on-time and off-time determine the range of duty cycle, and hence the range of boost output voltage. they do not affect whether the converter operates in ccm or dcm. for example, assume f sw is 2 mhz (t = 500 ns), t on(min) is 95 ns, and t off(min) is 75 ns. then: d (min) = t on(min) / t = 95 (ns)/ 500 (ns) = 19% d (max) = 1 ? t off(min) / t = 1 ? 75 (ns)/ 500 (ns) = 85% further, assume v vin is 4.0 to 5.5 v and v d1 is 0.4 v. then the possible v out is between 6.4 and 20.7 v. this is wider than the range required by individual regulators under all possible output combinations. therefore the minimum on-time and off-time are not limiting factors in output regulation. v out (min) = v vin (max) 1/(1 ? d(min)) ?v d1 = 6.4 v v out (max) = v vin (min) 1/(1 ? d(max)) ?v d1 = 26.7 v input disconnect switch the a8601 has a gate driver for an external pmos, in order to provide input disconnect protection function (figure11). during normal startup, the pmos is turned on gradually to avoid a large inrush current. in the event there is a direct short at the boost stage (either sw or out shorted to gnd), a high input current would cause the pmos to turn off. see the fault conditions sec- tion for details. the input disconnect current threshold is calculated by: i vin(max) = v ins(th) / r ins (12) where v ins(th) = 100 mv typical.
multiple-output regulator for automotive lcd displays a8601 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com under normal operation, the input current is protected by the cycle-by-cycle boost switch current limit, i sw(max) ,1.5 a (typ). only in the event of a direct short at the boost output (sw pin) will the input disconnect switch be activated. therefore the input disconnect current threshold should be set slightly higher than the switch current limit; for example, choose an r ins of 0.047 to set an i vin(max) of 2 a approximately. during a normal power-up sequence, as soon as en1 reaches high, the a8601 begins pulling the gate pin low by a 100 a current. how quickly the external pmos turns on depends on the gate capacitance c gs . if the gate capacitance is very low, the inrush current may momentarily exceed 2 a and trip the input dis- connect protection. in this case, an external c gs capacitor may be added to slow down the pmos turn-on. a typical value of 4.7 nf should be sufficient in most cases. when selecting the external pmos, check the following param- eters: ? drain-source breakdown voltage, v ( br)vdss , should exceed ?20 v ? gate threshold voltage should be fully conducting at v gs = ?4 v, and cut-off at ?1 v ? r ds(on) is rated at v gs = ?4.5 v or similar, not at ?10 v; derate for higher temperatures fault conditions the a8601 has extensive fault detection mechanisms, to protect against all perceivable faults at the ic level (pin open, pin short to gnd, pin short to neighboring pins, and so forth) and at the system level (external component open/short, component value changes from ?50% to +100%, and so forth). all feedback pins (fb1, fb2, fb3, and fb4) are monitored for overvoltage and undervoltage faults during normal operation. in case of an output short, or an open/short in the sense resistor network, the magnitude of the sensed voltage may make a sudden change that is either +20% over, or ?20% under the target volt- age. this will trigger the ovp/uvp fault and force the a8601 to shut down. ovp/uvp detections are disabled during the startup sequence. if any output fails to reach 90% of its target voltage within a time- out period, t ss(to) (50 ms typical), a fault is generated and then the a8601 shuts down. each regulator output (dvdd, avdd, vgh, vgl and vcom) is protected by its own independent overcurrent limit. when an output current exceeds its limit, the corresponding regulator goes into overcurrent protection mode to protect itself from damage. see figure 11 for illustrations of the protection characteristics. if the overcurrent condition persists for 50 ms, all regulators are turned off following the normal shutdown sequence. the same applies when there is an overvoltage fault detected at any of the feedback pins, except that the offending regulator is turned off immediately. the other outputs then shut down following normal sequence. in general, if a fault is detected, the a8601 halts operation and pulls the f a u l t pin low. it then attempts to restart operation after a delay, t restart , of 100 ms typical. internally there is a fault counter that keeps track of how many times any fault has occurred. if the fault counter reaches eight, the a8601 is com- pletely shut down. the fault counter is cleared by a completed shutdown sequence with en1 = en2 = low, or by a power reset (v vin drops below uvlo). during startup, all regulators go through a soft-start process, to prevent excessive inrush current from tripping ocp. the same applies to the turn-on of the exter- nal input disconnect pmos. target 0 033 100 output current, i dvdd , i avdd (%) 0 33 100 output current, i vcom (%) 0 100 output current, i vgh , i vgl (%) 00 v dvdd , v avdd v vcom v vgh, v vgl ta r g e t 3 v ta r g e t figure 11. overcurrent protection characteristics for dvdd, avdd, vcom, vgh, and vgl
multiple-output regulator for automotive lcd displays a8601 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pre-output fault detection when en1 turns on the a8601, a startup sequence is followed before the regulators are powered up. the sequence checks for extreme conditions and proceeds as described in table 1. general fault detection the faults described in table 2 are continuously monitored, whether during startup, normal operation, or shutdown. table 1. pre-output fault detection sequence step number step description fault description fault tripped? 1 check vin uvlo a8601 remains powered-down until v vin is above v uvlo . no 2 power-up internal rail a8601 initializes. no 3 check internal rail uvlo bias charges internal rail indefinitely, until v bias is above uvlo. no 4 check all fbx pins for short to gnd any fbx pin is detected as shorted after t ss(to) .yes 5 turn on input disconnect pull-down on gate pin does not reach < v vin ? 3.5 v after t ss(to) .yes 6 turn on dvdd fb1 pin does not reach >90% of target (2.4 v) after t ss(to) .yes 7 turn on avdd fb2 pin does not reach >90% of target (2.4 v) after t ss(to) .yes 8 turn on vgl fb3 pin does not reach >90% of target (?1.8 v) after t ss(to) .yes 9 turn on vgh fb4 pin does not reach >90% of target (2.4 v) after t ss(to) .yes 10 turn on vcom vcom pin does not reach >90% of target (v vinamp a vcom ) after t ss(to) .yes table 2. general fault detection fault description a8601 response to fault fault tripped? t tsd exceeded shutdown using shutdown sequence. fault counter increased by one, retry after t reset . yes; f a u l t set during t reset v fb1 , v fb2 , v fb3 , or v fb4 20% under target shutdown using shutdown sequence. fault counter increased by one, retry after t reset . yes; f a u l t set during t reset v fb1 , v fb2 , v fb3 , or v fb4 20% over target over-target regulator rail shut down without shutdown sequence. other regulator rails shut down using shutdown sequence. fault counter increased by one, retry after t reset . yes; f a u l t set during t reset v uvlo reached shutdown without using shutdown sequence. fault counter reset to 0, retry after t reset . no bias uvlo shutdown without using shutdown sequence. fault counter reset to 0, retry after t reset . no overcurrent limit for i dvdd , i avdd , i vcom , i vgh , or i vgl exceeded over-limit regulator rail goes into current fold-back or current limit. shutdown using shutdown sequence after t ocp(to) . fault counter increased by one, retry after t reset . yes; f a u l t set during t reset v ins(trip) exceeded shutdown without using shutdown sequence. fault counter increased by one, retry after t reset . yes; f a u l t set during t reset v sw(ovp) exceeded shutdown without using shutdown sequence. fault counter increased by one, retry after t reset . yes; f a u l t set during t reset i sw(max) 150% of ocp limit exceeded shutdown without using shutdown sequence. fault counter increased by one, retry after t reset . yes; f a u l t set during t reset
multiple-output regulator for automotive lcd displays a8601 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information output voltage selection each output voltage of dvdd, avdd, vgh, or vgl is selected using a simple voltage-sensing (resistor divider) network, as shown in figure 12. in actual implementation there is a small bias current that is flowing out from each positive fbx pin, and the direction is reversed for any negative fbx pin. this is necessary to detect any pin-open fault at an fbx pin. as shown in figure 13, a common bias current is injected into both the (+) and the (?) terminals of the operational-amplifier. due to the principal of superposition, the same set of equations as in figure 1 can be used to determine values for r1 and r2 in figure 13. v fb is the regulation voltage for the feedback pins, and it is spec- ified as 2.40 v for fb1 (dvdd), fb2 (avdd), and fb4 (vgh). for fb3 it is specified as ?1.80 v. the following considerations affect voltage selection: ? to cancel the offset error introduced by input bias currents, and to assure regulation loop stability, it is necessary to keep the external equivalent resistance, that is, the parallel resistance of r1 and r2, as follows: pin parallel resistance (k ) fb1 (dvdd) 10 1 fb2 (avdd) 25 1 fb3 (vgl) 50 2.5 fb4 (vgh) 50 2.5 ? to reduce the mismatch error of the sensing network, consider using 0.5% or 0.2% resistors for the resistor divider. ? to reduce effects of switching noises coupled into the fbx pins, add an external filter capacitor (typically a 47 pf mlcc) between the fbx pin and gnd. the capacitor should be placed as close as possible to the respective fbx pin. table 3 provides some examples of voltage sensing network component values, using e96 1% resistors. v out r1 r2 fbx a8601 v ref agnd 30 k + ? 5 k r z 25 k fbx a8601 v ref v ref agnd 30 k + ? 5 k output voltage sensing network equivalent circuit v out = v fb ( r 1 + r 2 ) / r 2 where: v fb = v ref r z = r 1 r 2 / ( r 1 + r 2 ) r 2 = r 1 v ref / ( v out ? v ref ) where: r z is 25 k and v ref is 2.4 v for avdd combining the two equations: r 1 = r z v out / v ref v out r1 r2 fbx a8601 v ref v bias i bias i bias agnd 30 k + ? 5 k r z 25 k fbx a8601 v ref v ref agnd 30 k + ? 5 k v bias i bias i bias output voltage sensing network equivalent circuit v out = v fb ( r 1 + r 2 ) / r 2 where: i bias = 0 a r z = r 1 r 2 / ( r 1 + r 2 ) r 2 = r 1 v ref / ( v out ? v ref ) where: r z is 25 k and v ref is 2.4 v for avdd based on the principle of superposition, the same equations can be used where i bias > 0 a: r 1 = r z v out / v ref figure 12. the output voltage sensing network and the equivalent circuit figure 13. the figure 12 circuits with the same bias cu rrent injected into both inputs of the operational amplifier
multiple-output regulator for automotive lcd displays a8601 25 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com output capacitance the boost stage requires an output capacitor, c out . use an mlcc with a capacitance of approximately 4.7 to 10 f and a voltage rating of 25 v. the temperature rating should be either x5r or x7r. do not use y5v, which has a very large variation with temperature. another point to note is the capacitance of mlcc is specified at a 0 v bias. to account for the degradation when the rated dc voltage is applied to an mlcc, the capaci- tance should be derated by as much as 50%. the derating factor is typically less if the capacitor is physically larger (for example, choose a 1206 package instead of an 0805) and has a higher volt- age rating (for example, 50 v instead of 25 v). to ensure system stability, each output (dvdd, avdd, vgl, vgh, and vcom) is required to have an external mlcc with a minimum output capacitance of 2 0.1 f. however, greater capacitance may be required to satisfy transient current require- ments. this is illustrated in figure 14. the avdd load current makes a step from 100 ma (steady state current) to 500 ma, for a duration of 3.2 s only. because the linear regulator for avdd takes a finite time to respond to this load change, the voltage dip is determined primarily by the output capacitance, c avdd . the corresponding voltage step, dv1, is determined by the esr of the output capacitor. when using an mlcc with very low esr (several m ), this drop is only several mv and can be omitted. table 3. examples of sensing network component values output [pin] v fbx (v) goal output values calculated resistor divider values actual resistor divider values calculated output values r z (k ) v out (v) r 1 (k ) r 2 (k ) r 1 (k ) r 2 (k ) r z (k ) v out (v) v out resistor divider error (%) dvdd [fb1] 2.4 10 3.3 13.75 36.67 13.7 36.5 9.96 3.3 0.02 avdd [fb2] 2.4 25 7 72.92 38.04 73.2 38.3 25.14 6.99 ?0.19 12.8 133.33 30.77 133 30.9 25.07 12.73 ?0.55 vgh [fb4] 2.4 50 14.5 302.08 59.92 300 59 49.3 14.6 0.71 24.6 512.5 55.41 511 54.9 49.57 24.74 0.56 vgl [fb3] ?1.8 50 ?5.4 150 75 150 75 50 ?5.4 0.00 ?11 305.56 59.78 309 60.4 50.52 ?11.01 0.08 note: use of series e96 1% resistors assumed. figure 14. avdd output voltage transient caused by a step change in load current avdd current, i avdd (ma) t 100 500 period = 31.8 s s 0 avdd voltage t target dv1 dv2 di = 400 ma dv1 = di esr dv2 = di dt / c avdd dt = 3.2
multiple-output regulator for automotive lcd displays a8601 26 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the second voltage step, dv2, is determined by the output capacitance. for example, assume c avdd = 20 f, then: dv2 = 0.4 (a) 3.2 ( s) / 20 ( f) = 64 mv operating with separate vin and boost supplies if necessary, the a8601 can be powered by a 5 v ldo for vin, while the boost stage can be powered by a different supply such as 3.3 v. this is illustrated in figure 15. the ldo for vin should have an output voltage of 5 v 10%. the ldo supply current is the sum of the a8601 bias current (approximately 6 ma at 2 mhz) and the dvdd output current. the boost supply voltage is independent from the vin voltage. a reasonable range for the boost supply is between 3.3 and 10 v. the boost supply current is determined by the output power of boost stage, as outlined in the thermal analysis section. the boost output voltage, v out , is always higher than its input, v boosts . therefore it is necessary to keep the boost supply voltage below a certain level. this can be determined for a boost converter as follows: v out = v boosts / (1 ? d ) (13) where d is the duty cycle. assume a boost pwm frequency of 2 mhz (period = 500 ns). the a8601 minimum on-time, t on(min) , is 95 ns worst-case. that results in a minimum pwm duty cycle of 19%. for a v boosts of 12 v, and a d of 0.19, the calculated v out would be 14.8 v. this is higher than the 14 v required by the a8601 output regulators in figure 15. higher v out levels result in excessive power loss and may trigger ovp at the sw pin. thermal analysis the thermal resistance, r ja , of the tssop-28 thermally enhanced package is 28c/w. for long term reliability, the package junction temperature should be kept at 150c or below. assuming a maximum ambient temperature of 85c, the power dissipation budget, p d (max), is: p d (max) = ( t j (max) ? t a (max)) / r ja (14) = (150 (c) ? 85 (c)) / 28 (c/w) = 2.3 w the power losses of the ic come from two main contributors, the boost stage and the linear regulators. these losses are calculated separately, then summed, as follows. to estimate the dissipation of the boost stage, calculate and sum the losses due to switching losses, p sw , and conduction losses in the switch, p cond : p d(boost) = p cond + p sw (15) 1. estimate the maximum output power for boost stage: p out (max) = v out (max) i out (max) (16) i out = i avdd + i vcom + i vgl + 2 i vgh (17) based on the average load current waveforms during normal operation (see characteristic performance section), the aver- age output current for the boost stage is estimated to be: i out = 140 (ma) +18.3 (ma) + 8.9 (ma) + (2 7.9 (ma)) 183 ma figure 15. typical dual supply application ld1 a8601 enable ins sw out v out 14 v c out v boosts 3.3 to 10 v v ins 8 to 16 v vin en1 en2 ldo 5 v dvdd fb1 avdd 12 v vgh 23 v vgl ?7 v vcom 4.2 v
multiple-output regulator for automotive lcd displays a8601 27 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com so at a maximum v out of 16 v, the maximum p out is: p out (max) = 16(v) 0.183 (a) = 3 w 2. estimate the maximum input current: i vin = p vin / v vin (18) p vin = p out / (19) where is efficiency (%). substituting into equation 10: i vin = (3 (w) / 0.85) / 4 (v) = 0.88 a. 3. estimate conduction loss for the internal switch: p cond = i 2 vin r ds(on) d (20) d = 1 ? v vin / ( v out + v d1 ) (21) where v d1 is the forward voltage drop of the external boost diode. subsituting into equation 20: p cond = (0.88 (a)) 2 0.7 ( ) [1 ? 4 (v) / (16(v) + 0.4 (v))] = 0.78 0.7 0.756 = 0.41 w where r ds(on) is 0.5 typical, plus 40% of typical for tem- perature compensation at 125c. 4. estimate switching loss for the internal switch: p sw = i sw v sw ( t r + t f ) f sw / 2 (22) where t r is the rise time, and t f the fall time, of v sw . subtitut- ing into equation 14: p sw = 0.88 (a) 16.4 (v) (10 (ns) + 10 (ns)) 2 (mhz) / 2 = 0.29 w assuming i sw equals i vin and v sw = v out + v d1 (23) substituting into equation 7: p d(boost) = p cond + p sw = 0.41 (w) + 0.29 (w) = 0.70 w therefore a total of 0.70w is dissipated on the boost stage. note that this analysis is done under the worst-case combination (maximum v out , minimum v vin , maximum f sw , and so forth). under typical operating conditions, the power loss is lower. the linear regulator power dissipations are the sum of the indi- vidual linear regulators: p d(linreg) = p ldo1 + p ldo2 + p ldo3 + p ldo4 + p ldo5 (24) referring to the functional block diagram notes, ldo1 is the regulator for dvdd, ldo2 is the regulator for avdd, ldo3 is the regulator for vgl, ldo4 is the regulator for vgh, and ldo5 is the regulator for vcom. estimate the maximum output power for each regulator as fol- lows, using the same worst-case values as for the boost stage calculations: 1. for dvdd: p ldo1 = ( v vin ? v dvdd ) i dvdd (25) substituting into equation 17: p ldo1 = (4 (v) ? 3.3 (v)) 20 (ma) = 0.03 w 2. for avdd (which is usually the largest contributor of power loss): p ldo2 = ( v out ? v avdd ) i ldo2 (26) i ldo2 = i avdd + i vcom (27) substituting into equation 18: p ldo2 = (16 (v) ? 10 (v)) (140 (ma) + 18.3 (ma)) = 0.95 w 3. for vgl (magnitude of vgl): p ldo3 = ( v out ? | v vgl |) | i vgl | (28) substituting into equation 20: p ldo3 = (16 (v) ? 12 (v)) 8.9 (ma) = 0.036 w 4. for vgh: p ldo4 = (2 v out ? v vgh ) i vgh (29) substituting into equation 29: p ldo4 = (2 16 (v) ? (18.5 (v)) 7.9 (ma) = 0.107 w 5. for vcom: p ldo5 = ( v avdd ? v vcom ) i vcom (30) substituting into equation 30: p ldo5 = (10 (v) ? (4.5 (v)) 18.3 (ma) = 0.101 w 6. finally, the ic consumes a bias current of approximately 6 ma from vin when en1 and en2 are both high. this adds power consumption of approximately 0.024 w at mini- mum v vin . substituting into equation 16, including the bias currrent factor: p d(linreg) = 0.03 (w) + 0.95 (w) + 0.036 (w) + 0.107 (w)+ 0.101 (w)+ 0.024 (w) = 1.25 w
multiple-output regulator for automotive lcd displays a8601 28 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 4. external component recommendations component manufacturer description external pmos renesas upa1830 v ( br)vdss = ?30 v (min), v gs(off) = ?2.0 v (typ), r ds(on) = 28 m (max) at v gs = ?4 v, sop-8 toshiba tpc8125 v ( br)vdss = ?30 v (min), v th = ?2.0 v (max), r ds(on) = 17 m (max) at v gs = ?4.5 v, sop-8 fairchild fds6675 v ( br)vdss = ?30 v (min), v gs(th) = ?3 v (max), r ds(on) = 20 mv (max) at v gs = ?4.5 v, sop-8 boost inductor vishay ihlp2020bzer3r3m01 l = 3.3 h, dcr = 79 m (typ), i heating = 3.3 a, 5.2 5.5 2 mm toko d63cb #a916cy-6r2m l = 6.2 h, dcr = 29 m (typ), i sat = 1.84 a, 6.2 6.3 3.5 mm tdk slf6045t-100m1r6-3pf l = 10 h, dcr = 39 m (typ), i sat = 1.6 a, 6 6 4.5 mm sumida cdr7d28mnnp-15? n l = 15 h, dcr = 65 m (typ), i sat = 2.1 a at 20c, 7.3 7.3 3 mm output diode on-semi mbr130 30 v, 1 a, v f = 0.47 v (typ) at i f = 1 a, sod-123 boost output capacitor murata grm31cr61e106ka12l 10 f, 25 v, x5r, 1206 negative charge pump external diode 1n4148w switching diode, 100 v, 0.15 a, c t = 2 pf, sod-123 rohm dan217 dual switching diode, 80 v, 0.1 a, ct = 3.5 pf, sot-346 therefore the sum of the power dissipations for all of the linear regulators is 1.25 w. the total power dissipation if the ic is then the sum of the boost stage and the linear regulators: 1.95 w (0.70 w plus 1.25 w). this corresponds to a temperature rise of 60c. at an ambient temperature of 85c, the junction temperature could reach 140c under the above worst-case conditions. component selection recommendations final component selection is dependent on many system param- eters, such as switching frequency, output power, and pcb area. the following recommendations should be used as a starting point only.
multiple-output regulator for automotive lcd displays a8601 29 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com i/o pin equivalent circuit diagrams 13 2 46 5 79 8 10 12 11 13 15 14 gate agnd 9.5 v 100 k v vin v vin v vin v vin v vin ins agnd 9.5 v 300 k vin agnd 9.5 v gate agnd 9.5 v 2 fb1 agnd 9.5 v 2 k v bias comp agnd 12 v 1.5 k v bias vcom agnd 9.5 v 2 k v avdd vinamp agnd 9.5 v 10 k v bias gndvcom agnd bias agnd 9.5 v 9.5 v 40 k fset _sync agnd 9.5 v 12 k v bias fault agnd en1 agnd 9.5 v 10 k 90 k 6.5 v agnd main esd ring substrate tie en2 agnd 9.5 v 10 k 90 k 6.5 v
multiple-output regulator for automotive lcd displays a8601 30 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 16 19 18 17 20 21 22 23 24 26 25 27 28 fb3 agnd 20 v 50 k 80 k v bias v vgl v vgh v bias cp12 cp11 v out vgl cp22 agnd 20 v 20 k 200 k v out agnd 20 v cp21 agnd 20 v v out fb4 agnd 2 k vgh agnd 30 v 240 k v out agnd 30 v 50 v 26 v agnd avdd agnd fb2 agnd 2 k v bias v out v out out agnd pgnd v bias agnd sw pgnd 125 k 1 pf
multiple-output regulator for automotive lcd displays a8601 31 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 28-pin tssop with exposed thermal pad a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 28x 0.65 bsc 0.25 bsc 2 1 28 9.700.10 4.400.10 6.400.20 gauge plane seating plane a terminal #1 mark area b for reference only; not for tooling use (reference mo-153 aet) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b c exposed thermal pad (bottom surface); dimensions may vary with device branded face 6.10 0.65 0.45 1.65 3.00 5.00 28 2 1 pcb layout reference view c 5.08 nom 3 nom reference land pattern layout (reference ipc7351 sop65p640x120-29cm); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5)
multiple-output regulator for automotive lcd displays a8601 32 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com revision history revision revision date description of revision rev. 1 september 27, 2012 change in i sw(max) and t off(min) copyright ?2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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